The functional testing of high-performance memory chips requires corresponding testing systems for the production of these memory chips. FIG. 1 shows a prior-art testing arrangement. An external testing device is connected via a control bus, a data bus and an address bus to an integrated memory chip and tests the functionality of the latter.
The external testing device addresses the memory cells to be tested within the integrated memory circuit and applies generated test patterns to the addressed memory cells via the data bus. Control signals for activating the integrated memory chip, such as read and write commands for example, are transmitted from the testing device via the control bus to the integrated memory chip. The test data written into the memory cells is subsequently read out again via the data bus and compared in the testing device with the originally generated test data, for checking the functionality of the memory cells contained in the integrated memory circuit, and evaluated. The higher the requirements imposed on the integrated memory circuits, the higher too the demands and capability of the external testing device for testing the memory chip. In many cases, no testing devices that have the required range of capabilities are available by the time production of the memory chips begins.
Therefore, integrated memory chips which have an inbuilt self-testing function to relieve the external testing device have been developed. FIG. 2 shows a prior-art memory chip with an integrated self-testing function BIST (BIST: Built-In Self-Test). In this case, the integrated self-testing circuit is likewise connected to the external testing device via the control bus, the data bus and the address bus. The address bus is also connected to an address decoder for the addressing of the memory area contained in the memory cell array, while the data bus is additionally connected to a data input/output management, which carries out the signal adaptation.
FIG. 3 schematically shows how the prior-art integrated memory chip represented in FIG. 2 is tested. In one test operating mode, it is decided whether the test concerned is a test of the functionality of the memory cells within the memory cell array or a test of the data exchange functionality of the entire integrated memory chip. The test of the functionality of the memory cell array is performed under the control of the inbuilt self-testing circuit, which generates the addresses of memory cells to be addressed within the memory cell array and applies them to the address decoder via the address bus. In addition, the internal self-testing circuit generates test data patterns, which are written into the addressed memory cells of the memory cell array via the internal data bus and the data input/output circuit. Subsequently, the data are read out from the addressed memory cells and evaluated by the integrated self-testing circuit with the generated test data patterns to evaluate the functionality of the memory cell array. The integrated self-testing circuit BIST subsequently informs the external testing device about the functionality of the memory cell array.
In a further test operating mode, the data exchange functionality of the entire integrated memory chip is tested, this being performed by the external testing device. In this case, the communication of the integrated memory chip with an external circuit is tested. For example, it is tested whether the signal connections and driver circuits of the integrated memory chip are functional and whether the memory chip is capable of communicating with external circuits. The test of the data exchange functionality of the memory chip is in this case performed under the control of the external testing device. Since modern memory chips operate at ever higher operating clock frequencies, the data exchange functionality of the integrated memory chip must likewise be carried out by the external testing device at a very high data transfer rate. The requirements imposed on the external testing device for testing the data exchange functionality of the high-performance memory chip are therefore likewise very high, so that correspondingly complex, expensive external testing devices have to be used. To some extent, highly complex testing devices of this type for the testing of high-performance memory chips are not available for testing the data exchange functionality of the memory chip in the case of new developments.
The object is therefore to provide a method of testing the integrated memory chip in which the data exchange functionality of the memory chip can be reliably tested with a conventional testing device which operates at a relatively low operating clock frequency and of providing an integrated synchronous memory which can be reliably tested with a conventional testing device.